Red Semiconductor

Red Semiconductor

There is a significant immediate opportunity in the embedded processor marketplace for a processor that can accelerate key maths used in crypto, autonomy and AI while leveraging existing tools, application software and expertise.

The dominant processor architectures today, like Arm, were designed pre-AI. Today a lot of AI is handled by bespoke processors, GPUs and NPUs. Right now in the embedded space, and in the future other Edge-segments, there is demand for:

• A more parallel processor architecture capable of running the fundamental mathematics of AI applications faster than legacy processors can,

• A single unified instruction set architecture (ISA) covering all aspects of the device,

• Access to a wide ecosystem of tools and software that can support the forecast trillion unit market,

• Secure data processing that enables Trust as more and more of our lives become trusted to AI enabled applications,

• A way of adding AI that is more efficient than using GPU or NPU.

RED Semiconductor’s new VISC (Versatile Intrinsic Structured Computing) microprocessor core is a step-change evolution of the emerging RISC-V processor. RISC-V enables the ISA and ecosystem, and VISC builds on that to deliver high performance AI processing and data security. VISC has stronger market fit than any standalone RISC-V solution, or any RISC-V +Vector or +GPU solution. VISC occupies the same conceptual ‘space’ in the design that a GPU or vector core would but delivers far better performance than either, both in silicon area and code density. 

VISC is initially being deliver for RISC-V but is ISA agnostic; we could deliver for Arm, X86, IBM or others: all legacy ISA’s that need to adapt to the AI-era. VISC comprises special instruction extensions to the base instruction set (Command-and-Control instructions to invoke VISC hardware functions, and Maths Toolbox instructions to accelerate key algorithms), and the VISC Microprocessor Core which decodes the special instruction and configures its issue and parallel execution stages to boost performance of algorithmic execution.